CS281 UONBI Structural Model for 32-Bit ALU Using the For Generate VHDL Statement

Question Description

Create a structural model for 32-bit ALU using the for generate VHDL statement.

Test the entity: you may want to create several testbenches that test various functionalities of the ALU.

2. Archive all relevant files for submission. Do not submit testbenches or waveforms used for intermediate testing.

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Lab 5 MIPS 32-bit ALU 100 Points CS 281 Systems Architecture I Overview In this assignment you will build a combinational model for an 32-bit ALU from 32 1-bit ALUs in VHDL using the for generate statement. Your 32-bit ALU will support the following operations: and, or, nand, nor, addition, subtraction, overflow detection, slt, zero flag. For this purpose you will have to modify the 1-bit ALUs to include ainvert circuitry and control. You are required to use for generate statement (see Chapter 14 of the Designer’s Guide to VHDL text) to create a structural model for the 32-bit ALU. Objective To become more comfortable with VHDL behavioral and structural models. To provide a better understanding of the construction of the MIPS ALU. To experience an advanced VHDL capability (for generate statement). Reading 1. 2. COD Appending B Section 5 (on CD) Chapter 14 of the Designer’s Guide to VHDL Review 1. 2. 3. Designer’s Guide to VHDL: Chapter/Sections – 1.1, 1.2, 1.4, 4.1, 5.1-5 Appendix B of Hennessey and Patterson. Sections 3.1 – 3.5 of Hennessey and Patterson. Specifications for the 32-bit ALU Provide support for: and, or, addition, subtraction, overflow detection, slt, zero flag. You are required to use for generate statement — if you manually instantiate 32 1-bit ALUs you will not receive full credit. HINT – this actually means you must write less code! What to do 1. 2. Create a structural model for 32-bit ALU using the for generate VHDL statement. Test the entity: you may want to create several testbenches that test various functionalities of the ALU. Archive all relevant files for submission. Do not submit testbenches or waveforms used for intermediate testing. Files 11:01:47 3/26/18 C:\USR\TC\CLASSES\CS281\CKNOTES\HOMEWORK\LABS\LAB5\Lab 5 MIPS 32-bit ALU.wpd 1/2 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. alu1.vhd alu1v.vhd alu32.vhd and_2.vhd and_3.vhd fulladder.vhd mux_2.vhd mux_4.vhd nand_2.vhd nand_3.vhd nand_4.vhd not_1.vhd or_2.vhd or_3.vhd or_32.vhd or_4.vhd tb_alu_32.vhd tb_alu1.vhd xor_2.vhd a32.bat What to hand in Your VHDL code, test results and description file should be submitted using the submission method specified in the Syllabus. Make sure you include: 1. Description file: Summary of what you did. Summarize programs you wrote, experiments performed, and files included. 2. Submit all your source code — document your code well. 3. Archive your files. 4. Output from running simulation on a sufficient set of inputs to test your FINAL code. Points distribution 1. 2. 3. The structural model for 32-bit ALU using the for generate VHDL statement (70 points) Correct use of the for…generate statement (20 points) The description file (10 points) 11:01:47 3/26/18 C:\USR\TC\CLASSES\CS281\CKNOTES\HOMEWORK\LABS\LAB5\Lab 5 MIPS 32-bit ALU.wpd 2/2 …
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