CS281 Drexel University MIPS 1 bit ALU Behavioral & Structural Models Lab 4

Question Description

Download, study and simulate the following models:

1. mux41b.vhd source for behavioral model of a 4 X 1 multiplexor.

2. half_adder_behavioral.vhd source for behavioral model of a half adder.

3. full_adder_behavioral.vhd source for behavioral model of a full adder.

4. full_adders.vhd source for structural model of a full adder.

5. and_2.vhd source for 2 input and gate.

6. or_2.vhd source for 2 input or gate.

7. xor_2.vhd source for 2 input exor gate.

8. alu1_behavioral.vhd source for behavioral model of the 1-bit ALU in Figure B.5.6 on page B.29

9. alu1_structural.vhd source for structural model of the 1-bit ALU in Figure B.5.6 on page B.29.

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Lab 4 MIPS 1 bit ALU 100 Points CS 281 Systems Architecture I Overview In this lab, we will create two models (behavioral and structural) of the 1-bit MIPS ALU on Figure B.5.6 on page B-29. The four components needed for the 1-bit ALU are: (1) 2-input and gate, (2) 2-input or gate, (3) a full adder, and (4) a 4 X 1 multiplexor. Last lab, we built a half adder and a 4 X 1 multiplexor. Before building the ALU, we will need to build a full adder. This will be done first by providing a behavioral model based on the logic circuit developed in class, and the secondly by providing a structural model using two half adders. Students will modify the 1-bit ALU to support subtraction and then modify that ALU to support overflow detection. The ALU that supports subtraction and the ALU that supports subtraction and overflow detection are pictured in the slides for the ALU Design lecture. Please note that support for slt and ainvert circuitry are not required and can be omitted for this lab — but they will be necessary for the Assignment 2 Part 2. Objective To become more comfortable with VHDL and simple behavioral and structural models. To provide a greater understanding of the construction of the MIPS ALU. Reading 1. Designer’s Guide to VHDL: Chapter/Sections – 1.1, 1.2, 1.4, 4.1, 5.1-5 2. Review appendix B.5 of Hennessey and Patterson. 3. Review sections 3.1 – 3.5 of Hennessey and Patterson. 4. Intro to VHDL Lecture slides. What To Do Download, study and simulate the following models: 1. mux41b.vhd source for behavioral model of a 4 X 1 multiplexor. 2. half_adder_behavioral.vhd source for behavioral model of a half adder. 3. full_adder_behavioral.vhd source for behavioral model of a full adder. 4. full_adders.vhd source for structural model of a full adder. 5. and_2.vhd source for 2 input and gate. 6. or_2.vhd source for 2 input or gate. 7. xor_2.vhd source for 2 input exor gate. 8. alu1_behavioral.vhd source for behavioral model of the 1-bit ALU in Figure B.5.6 on page B.29 9. alu1_structural.vhd source for structural model of the 1-bit ALU in Figure B.5.6 on page B.29. Create and test the following VHDL models: 11:01:36 3/26/18 C:\USR\TC\CLASSES\CS281\CKNOTES\HOMEWORK\LABS\LAB4\Lab 4 MIPS 1 bit ALU.wpd 1/3 1. 2. 3. 4. Behavioral model of 1-bit ALU that supports subtraction. Behavioral model of 1-bit ALU that supports overflow detection and subtraction. Structural model of 1-bit ALU that supports subtraction. Structural model of 1-bit ALU that supports overflow detection and subtraction. Files 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. alu1_behavioral.vhd alu1_structural.vhd alu1_sub_behavioral.vhd alu1_sub_ovf_behavioral.vhd alu1_sub_ovf_structural.vhd alu1_sub_structural.vhd and_2.vhd full_adder_behavioral.vhd full_adders.vhd half_adder_behavioral.vhd mux41b.vhd or_2.vhd tb_alu1_behavioral.vhd tb_alu1_behavioral-v2.vhd tb_alu1_structural.vhd tb_alu1_sub_behavioral.vhd tb_alu1_sub_ovf_behavioral.vhd tb_alu1_sub_ovf_structural.vhd tb_alu1_sub_structural.vhd xor_2.vhd a1b.bat a1b-pr.bat a1bv2.bat a1s.bat a1sb.bat a1sob.bat a1sos.bat a1s-pr.bat a1ss.bat What To Hand In (25 points each) 1. 2. 3. VHDL source for the modified behavioral and structural model of 1-bit ALU that supports subtraction. VHDL source for the modified behavioral and structural model of 1-bit ALU that supports overflow detection and subtraction. Test bench for and simulation waveforms produced by running the simulator for all 4 versions of your 1-bit ALU. The inputs to the ALU should be set in such a ways 11:01:36 3/26/18 C:\USR\TC\CLASSES\CS281\CKNOTES\HOMEWORK\LABS\LAB4\Lab 4 MIPS 1 bit ALU.wpd 2/3 4. so that all combinations of possible inputs are tested. A description file that thoroughly details all testing you have done, discusses your results and mentions any difficulties you may have encountered. Please follow the specifications for a description file. 11:01:36 3/26/18 C:\USR\TC\CLASSES\CS281\CKNOTES\HOMEWORK\LABS\LAB4\Lab 4 MIPS 1 bit ALU.wpd 3/3 …
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